Would it be the compiler/optimizer's job to figure out how to distribute the instructions in a superscalar setup?

@bryan based on my understanding, there are dedicated hardware units in the processor that detect data dependencies between instructions and check for idle execution units during runtime. using those results, the cpu can then execute independent instructions in parallel

@fdxmw & @bryan Yes, this seems to be the case based on what I found here: Instruction Window Tho it seems this is only looking at a "window" of instructions, so I'm wondering if this could be better done by the compiler as @bryan suggested?