It was mentioned in lecture that Intel kind of butchered the implementation of this, and had a ton of livelock issues

What is an example of security issues that can arise from hardware transactional memory implementations? It is hard for me to conceptualize security threats from such low-level systems.

A neat thing mentioned in the Intel Optimization guide is that reducing false sharing can also reduce the number of transactional aborts, as well as improving your cache efficiency. So padding to cache line size can kill two birds with one stone!