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gohan2021

During lecture, there is a very good point that even though data is part of write set (marked with W on the cache line), the data is not loaded into exclusive state because transaction hasn't finished yet. Therefore, when a data is loaded into exclusive state, transaction has already been committed. Marking data with write only add data to the write set to provide isolation property of transaction.

student1

I have a quick question regarding the coherence. Here basically we assume other processors that want to commit hold different cache and thus will send message using a bus. What will happen if we have two execution context sharing the same cache? In this case, will extra communication be needed?

kayvonf

@student1. Great question. A real implementation on a multi-threaded core would have to maintain information about which thread has loaded the line. Because as you noted, the read/write set is per transaction (a per thread concept), not per core.

If you are asking, what if so many lines are marked as a being in the read/write set for T0, and so there's no room in the cache for a line for the read/write set of T1 (e.g, due to capacity or lack of associativity)... you've identified a limitation of hardware implementations of TM. Basically if the cache must flush a line in the read/write set of a pending transaction, it basically has to abort that transaction... or stall the other transaction that need cache space.

However, if we ignore transactions and just talk about memory coherence. Then everything you know about coherence is true even for a multi-threaded core. Coherence involves communication between caches. If multiple cores, or multiple HW threads access the same cache, that is not relevant. The only think that is relevant is that the caches must communicate with each other to remain coherent.

martigp

I am a little bit confused about the V bit, what does this indicate? Since it is only a boolean I am not sure what extra information is given by this and why it is set for all 3 cache lines?

kayvonf

D and V are the standard "dirty" and "valid" bits for cache lines in any write-back cache. These exists even if this was a single processor system without cache coherence.

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