EE180 covers this very instruction! It's very strange, since it is TWO instructions that can be used to implement an atomic operation.
You implement LL/SC on a coherent processor by looking at the DIRTY bity of the cache line (not the actual memory address). What this means is that the "granularity" of the LL/SC instructions is at least a cache line, so there's a chance of false positives, unfortunately.
HOWEVER, here are a couple of advantages from LL/SC (taken from both experience and the excellently-written wikipedia page: https://en.wikipedia.org/wiki/Load-link/store-conditional)
- LL/SC separates the read instruction from the write instruction. This means you don't need to make a "special case" (as you do in the compare and swap instruction).
- Because of this, it's easier to implement a lock that doesn't generate as much bus traffic
- Finally, because LL and SC both take two arguments, it's easy to fit into two-instruction ISA's like MIPS 9which is what old computers such as the N64 ran!)
To implement a lock with LL/SC, (to my understanding), you would do something very similar to the "improved" CAS-Lock (the one where you mostly read and only occasionally write), where the reads would be LL and the writes SC.
EE180 covers this very instruction! It's very strange, since it is TWO instructions that can be used to implement an atomic operation.
You implement LL/SC on a coherent processor by looking at the DIRTY bity of the cache line (not the actual memory address). What this means is that the "granularity" of the LL/SC instructions is at least a cache line, so there's a chance of false positives, unfortunately.
HOWEVER, here are a couple of advantages from LL/SC (taken from both experience and the excellently-written wikipedia page: https://en.wikipedia.org/wiki/Load-link/store-conditional) - LL/SC separates the read instruction from the write instruction. This means you don't need to make a "special case" (as you do in the compare and swap instruction). - Because of this, it's easier to implement a lock that doesn't generate as much bus traffic - Finally, because LL and SC both take two arguments, it's easy to fit into two-instruction ISA's like MIPS 9which is what old computers such as the N64 ran!)
To implement a lock with LL/SC, (to my understanding), you would do something very similar to the "improved" CAS-Lock (the one where you mostly read and only occasionally write), where the reads would be LL and the writes SC.