Just to check my understanding, is it the case that if a line in one cache is in shared state, the line must be in either shared or invalid state in all other caches?

@jaez yes, as I believe can be seen from the next slide.

Suppose it's our very first time accessing a value that no other cache has. Is the starting point always shared or can we start in M if we have the intentions of writing to the value in the future.

evs, that is what MESI is for

Self-check: Why does a cache not have to generate a coherence message if it wants to move from the exclusive clean state (E) in MESI to the M state?

When is having an exclusive clean state better then directly moving from I to M?

Since the cache is in the E state, moving to M doesn't require passing a message over the bus because it is guaranteed that no other processors have this address in their caches, so the processor is free to modify the variable in its own private cache without informing everyone else.

This is beneficial when there is either 1 sequential program running or a parallel program where there is little data sharing. A common pattern is to read-modify-write. With the MSI protocol, the cache would read the address (I -> S, which issues a BusRd), and write to the address (S -> M, which issues a BusRdX). With MESI, the cache would read the address (I->E, which issues a BusRd), and write (E->M, no bus message). In the 1 sequential program or parallel program with little data sharing scenarios, we see that the MESI protocol has a significant advantage.

First part = Great!

Second part. In the one sequential program case, there would be no benefit to (E) since in both cases I->M or I->E->M there is only a single miss to memory, followed by a bunch of hits.

Trying to answer the second question: a good example is from later in lecture when we look at the implementation of locks with the test_and_set operation. While a thread is holding the lock, the cache line gets invalidated (on the other processor's memory) repeatedly and unnecessarily. Since test_and_set is considered a write operation for the cache coherence protocol, the exclusive clean state would be beneficial here, because it would reduce the amount of unnecessary memory traffic.

Are the MSI and MESI transitions those most commonly used by caches? I've learned about the MSI protocol in the past, but I was wondering if you had any suggestion on where to learn about the most recently used / most popular and important protocols.