It's fascinating that multi-socket systems with NUMA can also maintain the abstraction of a single, shared address space, considering it's so complex for a single chip. I imagine the chip itself has some support for essentially communicating between the different L3 caches, which aren't shared across sockets?

Doesn't this take a lot of storage to implement? Since the L3 cache is pretty big and this directory would scale linearly with the size of the cache.